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Contention-aware application mapping for Network-on-Chip communication architectures

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2 Author(s)
Chen-Ling Chou ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA ; Marculescu, R.

In this paper, we analyze the impact of network contention on the application mapping for tile-based network-on-chip (NoC) architectures. Our main theoretical contribution consists of an integer linear programming (ILP) formulation of the contention-aware application mapping problem which aims at minimizing the inter-tile network contention. To solve the scalability problem caused by ILP formulation, we propose a linear programming (LP) approach followed by an mapping heuristic. Taken together, they provide near-optimal solutions while reducing the runtime significantly. Experimental results show that, compared to other existing mapping approaches based on communication energy minimization, our contention-aware mapping technique achieves a significant decrease in packet latency (and implicitly, a throughput increase) with a negligible communication energy overhead.

Published in:

Computer Design, 2008. ICCD 2008. IEEE International Conference on

Date of Conference:

12-15 Oct. 2008

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