By Topic

Analogue CMOS continuous-time tapped delay-line circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

A microelectronic 20-stage tapped delay line consisting of cascaded lowpass filter amplifier stages has been demonstrated. The delay per tap is ~2.7 ns, and different versions have been optimised for pulsed and narrowband operation in the 30-70 MHz frequency range. Potential applications are in radar and adaptive antenna systems

Published in:

Electronics Letters  (Volume:31 ,  Issue: 21 )