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General algorithms for reduced-adder integer multiplier design

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2 Author(s)
Dempster, A.G. ; Westminster Univ., London ; Macleod, M.D.

The problem of reducing the number of adders required to perform shift-and-add multiplication is addressed for hardware and software applications. Algorithms invented for each of these applications are compared and found to have similar performances in general. Improved results are achieved by selecting the best design of the two

Published in:

Electronics Letters  (Volume:31 ,  Issue: 21 )