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Systolic architecture for inverse discrete cosine transform

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2 Author(s)
Yu-Tai Chang ; Inst. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu ; Chin-Liang Wang

The authors present an algorithm and its systolic implementation for computing the 1-D N-point inverse discrete cosine transform (IDCT), where N is a power of two. The architecture requires (N2-1)/3 multipliers and can evaluate one N-point IDCT every clock cycle. Owing to the features of regularity and modularity, the architecture is well suited to VLSI implementation. Compared with existing related arrays, the proposed algorithm has a better area-time performance. In addition, it can be extended to implementing the 2-D IDCT based on the row-column decomposition method

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Electronics Letters  (Volume:31 ,  Issue: 21 )