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Discrete-time cellular neural networks using distributed arithmetic

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An efficient digital architecture for the discrete-time cellular neural networks (DTCNNs) is proposed that employs the distributed arithmetic (DA). It consumes little silicon area because of the bit serial computation of DA, and offers higher speed operation than the analogue implementations of DTCNN. The proposed architecture has been implemented in a 0.8 μm CMOS technology

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Electronics Letters  (Volume:31 ,  Issue: 21 )