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Efficient Implementation of Floating-Point Reciprocator on FPGA

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2 Author(s)
Kumar Jaiswal, M. ; Dept. of Electr. Eng., IIT-Madras, Chennai ; Chandrachoodan, N.

In this paper we have presented an efficient FPGA implementation of a reciprocator for both IEEE single-precision and double-precision floating point numbers. The method is based on the use of look-up tables and partial block multipliers. Compared with previously reported work, the modules occupy less area with a higher performance and less latency. The designs trade off either 1 unit in last-place (ulp) or 2 ulp of accuracy (for double or single precision respectively), without rounding, to obtain a better implementation. Rounding can also be added to the design to restore some accuracy at a slight cost in area.

Published in:

VLSI Design, 2009 22nd International Conference on

Date of Conference:

5-9 Jan. 2009