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Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding

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3 Author(s)
Peng Zhang ; Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China ; Don Xie ; Wen Gao

This paper presents an efficient VLSI architecture for H.264/AVC content-adaptive binary arithmetic code (CABAC) decoding. We introduce several new techniques to maximize the parallelism of the decoding process, including variable-bin-rate strategy, multiple-bin arithmetic decoding, and efficient probability propagation scheme. The CABAC engine can ensure the real-time decoding for H.264/AVC main profile HD level 4.0. Synthesis results show that the multi-bin decoder can be operated up to 45 MHz, and the total logic area is only 42 K gates when targeted at TSMC's 0.18-mum process.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:17 ,  Issue: 3 )

Date of Publication:

March 2009

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