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A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes

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3 Author(s)
Hosseini, S.M.E. ; Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore ; Sann Chan, Kheong ; Wang Ling Goh

This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured low-density parity-check (LDPC) codes over additive-white Gaussian noise (AWGN) channels. The decoder, which has a serial architecture and moderate throughput, is a peripheral connected to the embedded Power PC processor of a Xilinx Virtex-II Pro FPGA and is managed by the processor. This method of hardware/software implementation provides the maximum flexibility for the development and rapid prototyping of the hardware-based simulator system. The decoding algorithm proposed in this paper belongs to the class of min-sum with correction factor in which the correction factor updates with the log-likelihood ratio (LLR) values.

Published in:

Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on

Date of Conference:

7-9 Nov. 2008

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