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The front-end digital encoder has become the bottleneck of the ultra-high speed flash ADCs. Pipelined digital encoder suites for 4-bit ultra high speed flash ADC is presented in this paper. It has two-stage pipelining to enhance the speed. The design is simulated and implemented using 0.18 mum UMC CMOS technology. The proposed encoder operates with 2.5 GSPS and consumes 0.8 mW. The proposed encoder effectively reduces the bubble induced error.
Date of Conference: 7-9 Nov. 2008