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A nonlinear sine-weighted digital-to-analog converter (DAC) can significantly reduces the power consumption and the complexity of direct digital frequency synthesizers (DDFSs). With the sine conversion implemented in the DAC, the phase-to-amplitude mapping (PAM) stage can be totally eliminated, thus drastically reduces the latency and increases the speed of the DDFS as the PAM stage is usually the speed bottleneck of a DDFS design. Utilizing quarter wave mapping technique, the simulated results of the DDFS with a 7-bit sine approximation using a modified binary-to-thermometer decoder, current switch and driver achieve a maximum spurious free dynamic range (SFDR) of 53 dBc at low synthesized output and better than 44 dBc across the whole Nyquist range when clocked at 4 GHz. Designed and simulated in 90 nm CMOS, this monolithic DDFS has 6 clock cycle latency and consumes only 462 mW when operating at 4 G sample/s.