An IP generator for quasi-cyclic LDPC convolutional code decoders

In this paper, the design and implementation of a high performance soft LDPC-CC decoder IP generator is presented. The proposed design is based on quasi-cyclic (QC) low-density parity-check matrices. These matrices not only simplify decoder design but also require less memory storage. A special digital processor is proposed to reduce the critical path and enhance the throughput. In addition, we have designed an IP generator and associated user interface that can take specifications of three parameters: iteration number, memory length, and code rate. With this generator, high-performance LDPC-CC decoders conforming to the user’s specifications can be generated effortlessly.