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An IP generator for quasi-cyclic LDPC convolutional code decoders

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6 Author(s)
Chun-Hao Liao ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei ; Jun-Wei Lin ; Yen-Shuo Chang ; Ching-Hao Yu
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In this paper, the design and implementation of a high performance soft LDPC-CC decoder IP generator is presented. The proposed design is based on quasi-cyclic (QC) low-density parity-check matrices. These matrices not only simplify decoder design but also require less memory storage. A special digital processor is proposed to reduce the critical path and enhance the throughput. In addition, we have designed an IP generator and associated user interface that can take specifications of three parameters: iteration number, memory length, and code rate. With this generator, high-performance LDPC-CC decoders conforming to the userpsilas specifications can be generated effortlessly.

Published in:

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Date of Conference:

Nov. 30 2008-Dec. 3 2008

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