By Topic

Design of off-chip capacitor-free CMOS low-dropout voltage regulator

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Xin Liu ; Coll. of Electron. Sci. & Eng., Jilin Univ., Changchun ; Shuai Wang ; Shuxu Guo ; Yuchun Chang

An off-chip capacitor-free CMOS low-dropout voltage regulator (LDO) for full on chip power management solution is presented. The proposed structure based on modified nested Miller compensation and transient enhancement network provides both fast load transient response and full load stability. For a pulsed load current between 0.5 mA and 50 mA, it is able to recover within ~3.5 mus and a less than 115 mV overshoots and undershoots of the output voltage is recorded for the most critical scenario. The total internal compensation capacitors are as small as 2.5 pF while the load capacitor can be as large as 100 pF. The idea has been implemented in CSMC 0.5 mum standard CMOS process and the total active chip area is 460 mum times 110 mum which makes it especially suitable for system-on-chip applications.

Published in:

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Date of Conference:

Nov. 30 2008-Dec. 3 2008