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A low-cost 1.2 V 5.14 mW phase-lock loop (PLL) quadrature frequency synthesizer compliant with the 2.4 GHz ZigBee standard (IEEE 802.15.4) has been implemented in 90 nm CMOS technology. In-phase and quadrature (I/Q) components exhibit a phase noise of -105.9 dBc/Hz at 1 MHz offset from the carrier. The PLL die area including decoupling capacitors and testing buffers is 209times422 mum2.
Date of Conference: Nov. 30 2008-Dec. 3 2008