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Incremental analysis is indispensible for efficient circuit optimization, as it analyzes the effect by the modified circuit part only instead of analyzing a whole circuit again from beginning. This paper presents a new incremental statistical static timing analysis (SSTA) method, called timing yield-based incremental analysis (TYIA). TYIA uses the probability that the gate timing slack is non-negative to prune the timing change propagation after a gate replacement. In the experimental results using ISCAS-85 benchmarks, TYIA showed 2~5 times better accuracy in timing yield analysis at comparable efficiency, when compared to the existing incremental SSTA methods.