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In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for system-on-chip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI reduction for system applications. Besides, the proposed ADSSCG employs an ultra-low-power digitally controlled oscillator (DCO) to save overall power consumption to 560 muW (@400 MHz) and the peak EMI power reduction is large than 25 dB. In addition, the proposed ADSSCG can be implemented only with standard cells; as a result, the area can be saved without any passive component, and making it easily portable to different processes and very suitable for SoC applications.
Date of Conference: Nov. 30 2008-Dec. 3 2008