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A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC

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5 Author(s)
Shang-Quan Liang ; Inst. of VLSI design, Hefei Univ. of Technol., Hefei ; Yong-Sheng Yin ; Hong-hui Deng ; Yu-kun Song
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A low power consumption, high speed op-amp is designed for a 10-bit, 100 MSPS parallel pipeline A/D converter. The op-amp plays an important role in the ADC, because its conversion rate and power consumption are limited by the performance of the op-amps. The designed ADC in this paper employs parallel architecture based on double sampling technology, and shares the op-amp between the same stages of two channels of the ADC. The op-amp consists of fully-differential telescopic cascode OTA and single common-source amplifier with cascode compensation technology. The op-amp implementation employs TSMC 0.25 um BSIM3v3 mixed-signal CMOS process model. The open-loop DC gain is 88.4 dB, the phase margin is 62.6deg, the unity gain bandwidth is 500.4 MHz with the load capacitor of 0.4 pF, and the power consumption is 2.6 mW. Transient simulation indicates a settling time of 11.3 ns with the feedback factor of 1/2.

Published in:

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Date of Conference:

Nov. 30 2008-Dec. 3 2008