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This paper presents a new CMOS amplifier with high common-mode rejection ratio (CMRR) and low offset, dedicated to integrated sensors, using total continuous-time design technique but without the need of trimming. This is based on cascading two high-gain differential stages to form a composite front-end gain stage for enhancing CMRR as well as reducing systematic errors, and incorporating an averaging layout technique to reduce the random mismatch errors. Powered by a total 3.3 V supply, measurements on 15 samples have shown that the mean and standard deviation of the input-referred offset are 50.4 muV and 0.678 mV respectively. The proposed amplifier has also achieved CMRR greater than 110 dB (0 - 150 Hz), offset drift less than 0.8 muV/degC for temperature ranging from -55degC to +125degC, input-referred noise less than 17.47 nV/radic(Hz) at 1 kHz and active area of 0.117 mm2 in a 0.6 mum CMOS technology.