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High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms

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4 Author(s)
Guntoro, A. ; Dept. of Electr. Eng. & Inf. Technol., Tech. Univ. Darmstadt, Darmstadt ; Momeni, M. ; Keil, H.-P. ; Glesner, M.

In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse Discrete Wavelet Transforms (DWTs). Our architecture is based on processing elements which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, IEEE 754 floating-point arithmetics are used to compute the transformation. We also consider the normalization step which takes place at the end of the forward DWT or at the beginning of the inverse DWT. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 8 processing elements and 2 times 256 words memory in a 0.18-mum technology is 2.2 mm2 and the estimated operating frequency is 340 MHz.

Published in:

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Date of Conference:

Nov. 30 2008-Dec. 3 2008