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Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n,2n+1−1,2n−1)

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4 Author(s)
Su-Hon Lin ; Grad. Sch. of Eng. Sci. & Technol., Nat. Yunlin Univ. of Sci. & Technol., Douliou ; Ming-hwa Sheu ; Chao-Hsiang Wang ; Yuan-Ching Kuo

The moduli set M1=(2n,2n+1-1,2n-1) which is free of 2a+1 modulus is profitable to construct a high-speed residue number system (RNS). In this paper, we derive a reduced-complexity residue-to-binary conversion algorithm for M1 by using new Chinese remainder theorem (CRT). The resulting converter architecture mainly consists of carry-save adders (CSAs), modular adders and multiplexer (MUX) which is suitable for an efficient VLSI implementation. Under the same dynamic range (DR) requirement, the proposed converter design is significantly more efficient than the latest design for M1 with respect to area-time (AT), time-power (TP) and area-time-power (ATP) products. Based on UMC 0.18 um CMOS cell-based technology, the chip area for 16-bit residue-to-binary converter is only 931times931um2 and the working frequency is 135 MHz.

Published in:

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Date of Conference:

Nov. 30 2008-Dec. 3 2008