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This paper describes an ESD verification methodology that is applied at several points in the design process. By identifying ESD reliability hazards at each step in the design flow, the amount of redesign needed to address ESD reliability issues is greatly reduced. The checker efficiently computes power bus parasitic resistances, allowing it to be used during floor planning when the library is unavailable; it finds the three shortest ESD paths between any two external pads, allowing the checker to be used during IO ring placement before completion of the chip layout; it processes the GDS file and checks the voltage drop between any two ESD devices; it simulates the voltage drop across each ESD device in the discharge path in order to detect ESD design flaws. The ESD checker can be used with or without the actual extracted netlist, i.e., with either a DSPF or a DEF file.