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In this paper, a cumulative electrostatic discharge (ESD) induced degradation of power-rail ESD clamp circuits in high-voltage (HV) CMOS/DMOS technologies was proposed. The IC which was verified by in-house test that it can pass Human-Body-Model (HBM) ESD 2 kV and Machine-Model (MM) ESD 200 V criteria, on the basis of test procedure described in JEDEC standards, was reported that it canpsilat pass negative-to-VDD (ND-mode) HBM 1.8 kV test with finer voltage steps, which originally was defined as an optional choice to obtain a more accurate failure threshold. Failure analysis (FA) revealed that one of the power-rail ESD clamp device was damaged. Corroborated by the experimental results, only HV N-type devices are vulnerable to this kind of cumulative ESD test and show poor reliability. Replacing the power-rail ESD clamp by the device with much higher HBM ESD immunity than original one was verified to be an effective solution to help the IC pass HBM 2 kV with the severest testing condition.