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Flexible LDPC decoder architecture for high-throughput applications

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3 Author(s)
Sangmin Kim ; Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN ; Sobelman, G.E. ; Hanho Lee

In this paper, we present a flexible high-throughput LDPC decoder architecture that can support different code rates and block sizes in wireless applications such as IEEE 802.11n, IEEE 802.16e, and IEEE 802.15.3c standards. Several flexible LDPC decoders have been presented in the literature but their throughput (less than 640 Mbps) is limited due to block-serial scheduling of the decoding computations. The proposed architecture is based on a block-parallel scheduling scheme using a layered decoding method. To achieve higher throughput, check node-based processes are implemented in a fully parallel architecture and the memory is partitioned into a number of banks. System flexibility is achieved by allowing the check node-based units and the memory banks to be configured according to the code rate and block size of the LDPC code of interest.

Published in:

Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on

Date of Conference:

Nov. 30 2008-Dec. 3 2008