By Topic

Virtualizing and sharing reconfigurable resources in High-Performance Reconfigurable Computing systems

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Esam El-Araby ; NSF Center for High-Performance Reconfigurable Computing (CHREC), ECE Department, The George Washington University, 801 22nd Street NW, DC 20052, USA ; Ivan Gonzalez ; Tarek El-Ghazawi

High-performance reconfigurable computers (HPRCs) are parallel computers but with added FPGA chips. Examples of such systems are the Cray XT5h and Cray XD1, the SRC-7 and SRC-6, and the SGI Altix/RASC. The execution of parallel applications on HPRCs mainly follows the single-program multiple-data (SPMD) model, which is largely the case in traditional high-performance computers (HPCs). In addition, the prevailing usage of FPGAs in such systems has been as co-processors. The overall system resources, however, are often underutilized because of the asymmetric distribution of the reconfigurable processors relative to the conventional processors. This asymmetry is often a challenge for using the SPMD programming model on these systems. In this work, we propose a resource virtualization solution based on partial run-time reconfiguration (PRTR). This technique will allow sharing the reconfigurable processors among the underutilized processors. We will present our virtualization infrastructure augmented with an analytical investigation. We will verify our proposed concepts with experimental implementations using the Cray XD1 as a testbed. It will be shown that this approach is quite promising and will allow full exploitation of the system resources with fair sharing of the reconfigurable processors among the microprocessors. Our approach is general and can be applied to any of the available HPRC systems.

Published in:

2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications

Date of Conference:

16-16 Nov. 2008