FPGA Implementation of Real-Time Edge-Preserving Filter for Video Noise Reduction

In this paper, VLSI architectures and FPGA implementation for edge-preserving filter are presented. We proposed two architectures for edge preserving filter: full parallel pipelined and structure-shared architectures. The edge-preserving filter uses adaptive coefficient mask based on the intensity distance in filter blocks. Compared with the bilateral filter, the proposed edge-preserving filter provides significantly noise reduction. We implement the proposed architecture on Cyclone II EP2C70F896C8 FPGA device from Altera Corp. Our experiments show that the PSNR improvement is up to 5.3 dB for Gaussian noisy images.