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A Flexible DSP Architecture for MIMO Sphere Decoding

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2 Author(s)
Chia-Hsiang Yang ; Dept. of Electr. Eng., Univ. of California at Los Angeles, Los Angeles, CA, USA ; Markovic, D.

This paper presents the architecture and circuit design of a sphere decoder for agile multi-input multi-output (MIMO) communication systems. Algorithm and architecture co-design is used to reduce hardware complexity, which enables the proposed sphere decoder to support larger antenna-array sizes and higher order modulations. The proposed architecture is also capable of processing multiple frequency subcarriers for orthogonal frequency-division multiplexing (OFDM) based systems. A 20 times area reduction is achieved, even without interleaving of subcarriers compared to the direct-mapped architecture. The sphere decoder supports multiple configurations: antenna arrays from 2 times 2 to 16 times 16, constellation sizes from binary phase-shift keying (BPSK) to 64-QAM (quadrature-amplitude modulation), and 16-128 subcarriers. The peak estimated data rate exceeds 1.5 Gbits/s of ideal throughput in a 16-MHz bandwidth. The core area is estimated at 0.31 mm2 in a standard 90-nm CMOS technology. The estimated power consumption is 33 mW in the 16 times 16 64-QAM mode at 256 MHz from a 1-V supply voltage.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:56 ,  Issue: 10 )

Date of Publication:

Oct. 2009

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