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Within this work an 11-bit digital-to-analog converter (DAC) with a combined capacitor and resistor network is presented. The proposed topology contains a series of resistors for the lower 6-bit and a binary-weighted capacitor network for the higher 5-bit. Due to this two-stage design approach, area is reduced by a factor of 12 compared to a simple binary-weighted network requiring 211 unit capacitors. In order to achieve both, high conversion rate plus 11-bit accuracy, additionally to the two-stage design, device matching is improved using a series of two capacitors instead of one for the basic cell. Thus the differential non linearity (DNL) is reduced, as a factor of two in device matching is gained. For the output range of 2.5 V to 3.7 V a DNL<0.8LSB, an integral non linearity (INL) of 1.68LSB, and a conversion rate of 20 MS/s are achieved at a power consumption of ~8 mW at Vcc=5 V. The DAC is realized in a 0.6 Â¿m BiCMOS process with an active area smaller by a factor of nine compared to the total chip size of 1600Ã915 Â¿m2.