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Physical Design Automation at Transistor Level

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1 Author(s)
Reis, R. ; Inst. de Inf., Univ. Fed. do Rio Grande do Sul, Alegre

The paper presents a new approach for the physical design of integrated circuits where all logic cells are designed on the fly, without the limitations that exists when using a cell library (number of functions, number of transistors, transistor sizing, area and power consumption). A cell generator allows the automatic design of cells having any transistor network (using simple gates or static CMOS complex gates - SCCG) and any transistor sizing. When the size of the transistor should be bigger than the cell height, the tool is able to do transistor folding. As the designer is free from the limitations of a cell library, it is possible to do a deep logic minimization where all needed logic cells will be generated on the fly. This allows a reduction on the number of needed transistors to implement a circuit. As consequence, the static power consumption will also be reduced. The cell generator provides cells with a compacted layout, allowing a significant transistor density. It is presented physical design automation strategies related to transistor topologies, management of routing in all layers, VCC and Ground distribution, clock distribution, contacts and vias management, body ties management, transistor sizing and folding and the how these strategies can improve the layout optimization. Some results are compared with the ones obtained with traditional standard cells tools (vendor's tools), showing the gain in area, delay and power consumption. The flexibility of the approach can also let the designers to define the layout parameters to cope with problems like tolerance to transient effects, yield improvement, printability, etc. The designer can also manage the sizing of transistors to reduce power consumption, without compromising the clock frequency.

Published in:

NORCHIP, 2008.

Date of Conference:

16-17 Nov. 2008

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