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New memory-efficient hardware architecture of 2-D dual-mode lifting-based discrete wavelet transform for JPEG2000

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2 Author(s)
Chih-Hsien Hsia ; Dept. of Electr. Eng., Tamkang Univ., Taiwan ; Jen-Shiun Chiang

This work presents new algorithms and hardware architectures to improve the critical issues of the 2-D dual-mode (supporting 5/3 lossless and 9/7 lossy coding) lifting-based discrete wavelet transform (LDWT). The proposed 2-D dual-mode LDWT architecture has the advantages of low-transpose memory, low latency, and regular signal flow, which is suitable for VLSI implementation. The transpose memory requirement of the N × N 2-D 5/3 mode LDWT is 2N, and that of 2-D 9/7 mode LDWT is 4N. According to the comparison results, the proposed hardware architecture surpasses previous architectures in the aspects of lifting-based low-transpose memory size. It can be applied to real-time visual operations such as JPEG2000, MPEG-4 still texture object decoding, and wavelet-based scalable video coding.

Published in:
Communication Systems, 2008. ICCS 2008. 11th IEEE Singapore International Conference on

Date of Conference: 19-21 Nov. 2008

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