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VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor

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4 Author(s)
Shih-Chang Hsia ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Bin-Da Liu ; Jar-Ferr Yang ; Bor-Long Bai

We propose the pipelined VLSI architecture and modular design to realize the coefficient-by-coefficient two-dimensional inverse discrete cosine transform (2-D IDCT) suggested by Yang, Bel, and Hisa (see ibid., vol.5, no.1, p.25-30, 1995). Based on parallel processing, the architecture of this chip is designed with a five-stage pipeline to meet the speed requirement for real-time applications. The key building modules of this chip include a generator of cosine angle index, a pipelined multiplier, and a matrix accumulator core. Satisfying the IEEE standard of 2-D IDCT in computational accuracy, this IDCT chip, which can work at a clock rate of higher than 50 MHz, is implemented by the CMOS technology in a reasonable die size. With modular and regular structures, the IDCT VLSI chip can be operated in a progressive transform mode. In a real video decoding system, the average pixel-rate of the proposed 2-D IDCT chip achieves over 150 MHz for decoding intraframes and up to 400 MHz for decoding interframes

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Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:5 ,  Issue: 5 )