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A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.