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A compact real-time vision system using integrated memory array processor architecture

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3 Author(s)
Okazaki, S. ; Inf. Technol. Res. Labs., NEC Corp., Kanagawa, Japan ; Fujita, Y. ; Yamashita, N.

This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP board, a video board and a host workstation. The IMAP board consists of eight highly-integrated IMAP LSIs and a dedicated control LSI (RVSC). The IMAP chip integrates 2 Mb image memory and 64 processing elements that operate in the SIMD mode. The RVSC chip performs global data operations efficiently without interactions with the host workstation, as well providing an instruction stream to the IMAP chips. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing tasks are carried out within about 0.1-0.7 ms, which is about 50-300 times faster than the video frame rate

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Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:5 ,  Issue: 5 )