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An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management

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8 Author(s)
Vinod Ramadurai ; IBM Syst. & Technol. Group, Essex Junction, VT ; Harold Pilo ; John Andersen ; Geordie Braceras
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This paper describes an 8 Mb SRAM test chip that has been designed and fabricated in a 45 nm Silicon-On-Insulator (SOI) CMOS technology. The test chip comprises of sixteen 512 kb instances and is designed for use as the principal compilable one-port embedded-SRAM block in a 45 nm ASIC library. Challenges associated with SRAM cell design in SOI are overcome and resulted in a cell size of 0.315 mum2 . The paper introduces two circuit techniques that address the AC and DC power consumption issues facing today's embedded-SRAMs. The first technique addresses AC power dissipation by utilizing a two-stage, body-contacted sensing scheme that, among other improvements, achieves a 68% improvement in read power under constant voltage and frequency compared to the previous generation macro . The second technique addresses the DC power consumption by introducing a single-device, header based dynamic leakage suppression scheme that reduces total macro leakage power by 38% with no wake-up cycle requirements.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 1 )