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A Resonant Global Clock Distribution for the Cell Broadband Engine Processor

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10 Author(s)
Steven C. Chan ; Res. Center. He is now with TSMC, San Jose, CA ; Phillip J. Restle ; Thomas J. Bucelot ; John S. Liberty
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Resonant clock distributions have the potential to save power by recycling energy from cycle-to-cycle while at the same time improving performance by reducing the clock distribution latency and filtering out non-periodic noise. While these features have been successfully demonstrated in several small-scale experiments, there remained a number of concerns about whether these techniques would scale to a product application. By modifying the Cell broadband engine processor to incorporate a large resonant global clock network, power savings with full functionality is demonstrated over a 20% range in clock frequencies, and a 6-8 Watt power savings at 4 GHz. This was achieved by changing one wiring level and adding an additional thick copper level to create inductors and capacitors.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:44 ,  Issue: 1 )