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A single chip video signal processing architecture for image processing, coding, and computer vision

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5 Author(s)
J. Goodenough ; Dept. of Electron. & Electr. Eng., Sheffield Univ., UK ; R. J. Meacham ; J. D. Morris ; N. Luke Seed
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A new VLSI (CMOS) architecture for an internally multiprocessing, single chip, SIMD-based video signal processor (VSP) is presented. The limitations of extended DSP architectures and conventional array processors are discussed in the context of image processing, coding and computer vision. How this gives rise to the architecture is described. Architectural flexibility is provided by the integration of a novel array-based processing core, together with a RISC processor, intelligent memory interface processor, and internal cache RAM. The array core architecture is a second generation, enhanced array whose key features are: 2 b datapath, dual processor mesh-connected array planes and combined SIMD/systolic functionality. The core is optimized for 2-D windowed operations, particularly 2-D multiply-accumulation and transforms. The device is expected to operate at 80 MHz on low voltage silicon and deliver real-time performance across a range of target applications

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IEEE Transactions on Circuits and Systems for Video Technology  (Volume:5 ,  Issue: 5 )