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This paper presents a CMOS imager chip that is aimed at subretinal implantation for partially restoring human vision. It has low supply voltage (plusmn 2 V) and all DC free terminals for long life wired operation. Stimulation voltage is increased to approximately 4 Vpp by low voltage drop design. 40 x 40 pixel cells including light sensors, amplifiers, control logic and electrode drivers are addressed sequentially to improve power consumption and spatial resolution of perception. Pad count is limited to 6, which requires a specific test procedure. The 3 x 3 mm2 design is fabricated in a 0.35 mum CMOS technology optimized for optical performance.
Date of Publication: Jan. 2009