By Topic

Interconnect capacitance characterization based on charge based capacitance measurement (CBCM) technique for DFM applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)

Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated circuits. This paper presents a test structure and a characterization method based on charge based capacitance measurement technique. The method could be implemented to study the variability of physical parameters such as interlayer dielectric (ILD) thickness and interconnect drawn width reduction, which can in turn be used in process/device modeling for design-for-manufacturing applications.

Published in:

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Date of Conference:

20-23 Oct. 2008