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Interconnection parasitic capacitance is the dominant delay and noise source in modern integrated circuits. This paper presents a test structure and a characterization method based on charge based capacitance measurement technique. The method could be implemented to study the variability of physical parameters such as interlayer dielectric (ILD) thickness and interconnect drawn width reduction, which can in turn be used in process/device modeling for design-for-manufacturing applications.
Date of Conference: 20-23 Oct. 2008