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Low power circuits for NoC-based SoC design

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3 Author(s)
Song, Z. ; Sch. of Comput. Sci. & Technol., Harbin Eng. Univ., Harbin, China ; Guangsheng Ma ; Song, D.

In large-scale system-on-chips (SoCs), the power consumption on the communication infrastructure should be minimized for reliable, feasible, and cost-efficient implementations. An energy-efficient network-on-chip (NoC) is necessary for application to high performance SoC design. Various low-power circuits are designed, and implemented in each open system interconnection layer. Low-swing serial link and source-synchronous serial communication in physical layer and low-energy serial link coding in data-link layer are designed and realized on the NoC. Partially activated crossbar and Mux-Tree based round-robin scheduler are also designed to reduce the power consumption in network layer. Experiment on these low-power circuits demonstrate that the NoC power dissipation is reduced by 38%.

Published in:

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Date of Conference:

20-23 Oct. 2008