Design and test results of a front-end ASIC for radiation detectors

A front-end ASIC for semiconductor radiation detectors is presented. It is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper, and a Peak Detect and Hold (PDH) circuit. Poly-resistor is used as source degeneration component to reduce the noise of current source in the CSA. The ASIC has been designed in a 0.5um CMOS DPTM technology and tested with Verigy 93000. The gain (PDH excluded) is 78.5mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 800-900e. The power dissipation without the output buffer is about 2.6mW.