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A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of 1 MHz and settles in less than 180 Â¿s is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling, integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency calibration (AFC) of programmable dichotomizing coarse tuning technology is integrated. The novel AFC structure uses pulses of 2n times of the PFDÂ¿s reference frequency for counting and comparison. Two multi-band voltage controlled oscillators, which cover 866 to 1468 MHz and 1282 to 1892 MHz separately, are implemented so as to reduce VCO output noise and power consumption by reducing VCO gain on each frequency turning curse. I/Q carriers are generated by VCO output divided by 2. Fabricated in 0.18-Â¿m CMOS technology, the PLL achieves phase noise of less than -132 dBc/Hz at 1.45 MHz offset.