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A novel decoder for Complementary Code Keying (CCK) modulation is proposed in this work. Compared to the parallel decoder architecture based on Fast Walsh Transform (FWT), the presented pipelined architecture has better hardware sharing and utilization efficiency, as well as smaller area. Its hardware area for finding the maximum decoding output value is minimized by employing a low-complexity on-the-fly comparator that takes advantage of the sequentially incoming chips and the pipelined data flow. Also, the proposed design consumes only 50.6 Â¿w at 11MHz based on UMC 0.18-Â¿m process, which is much lower than the conventional FWT-based architecture. Thus it is a low-power and low-area solution for the design of a high-performance 802.11b system.