By Topic

Low-k breakdown improvement in 65nm dual-damascene Cu process

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Wang, F. ; Logic Technol. Dev., Semicond. Manuf. Int. Corp., Beijing, China ; Howard Gan ; Linlin Zhao ; Zheng, K.
more authors

Leakage and breakdown characteristics of low-k dielectrics are becoming increasingly important reliability issues for Cu interconnects as device dimensions are scaled. Especially, in 65 nm dual-damascene Cu process, low-k dielectric has difficulty in meeting a breakdown spec of 50 V on cumulative curve at 0.1% intersection. Both dual-damascene metal dimension process uniformity control and interface integrity between Cu and NDC cap layer (SiCN) control are highly important in the 65 nm low-k dielectric breakdown reliability.

Published in:

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Date of Conference:

20-23 Oct. 2008