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A novel zero-aware read-static-noise-margin-free SRAM cell for high density and high speed cache application

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4 Author(s)

To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM cell using same design rules. Simulation result in standard 0.25 ¿m CMOS technology shows purposed cell has correct operation during read/write and idle mode. The average delay of new cell is 20% smaller than a six-transistor SRAM cell.

Published in:

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Date of Conference:

20-23 Oct. 2008