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High performance MOSFET scaling study from bulk 45 nm technology generation

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3 Author(s)
Xingsheng Wang ; Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow, UK ; Roy, S. ; Asenov, A.

This paper presents a MOSFET scaling study based on the current 45 nm technology generation. The study is based on a real 35 nm gate length design, to which the simulation tools are carefully calibrates. Features such as strain enhancement, and high-¿ / metal gates are included in the simulations, which then exhibit equivalent performance to state-of-the-art bulk devices. Realistic choices of device dimensions and doping profiles are made for the scaled devices, which indeed demonstrate the benefits from scaling and the introduction of technology boosters.

Published in:

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Date of Conference:

20-23 Oct. 2008

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