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This paper presents a MOSFET scaling study based on the current 45 nm technology generation. The study is based on a real 35 nm gate length design, to which the simulation tools are carefully calibrates. Features such as strain enhancement, and high-Â¿ / metal gates are included in the simulations, which then exhibit equivalent performance to state-of-the-art bulk devices. Realistic choices of device dimensions and doping profiles are made for the scaled devices, which indeed demonstrate the benefits from scaling and the introduction of technology boosters.