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Modeling the gate current 1/f noise and its application to advanced CMOS devices

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7 Author(s)
Crupi, F. ; DEIS, Univ. of Calabria, Rende, Italy ; Magnone, P. ; Iannaccone, G. ; Giusi, G.
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In this work we propose an analytical model for the gate current 1/f noise in CMOS devices. The model is based on a simple idea: one electron trapped in the dielectric switches-off the tunneling through the oxide over an effective blocking area. The model allows evaluating the effective trap density inside the gate dielectric as a function of energy from measurements of the gate current 1/f noise versus gate voltage. Experimental data on advanced CMOS devices confirm the validity and the usefulness of the proposed model.

Published in:

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Date of Conference:

20-23 Oct. 2008

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