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Twin Butterfly High Throughput Parallel Architecture FFT Algorithm

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2 Author(s)
Wang Chao ; Sch. of Inf. Eng., Univ. of Sci. & Technol. Beijing, Beijing ; Han Yun Peng

A novel parallel memory accessing for decimation-in-time twin butterfly parallel architecture radix-4 FFT algorithm is proposed, which is based on "in-place" principle and allows conflict-free access to the 8 operands needed for calculation of the twin butterfly distributed over 8 parallel memory modules. Data and twiddle factor address generation algorithm and store scheme are described detailed. Comparison with conventional methods is also presented.

Published in:

2008 International Symposium on Information Science and Engineering  (Volume:2 )

Date of Conference:

20-22 Dec. 2008