By Topic

Verification of Controller Synthesis Based on Completely Specified Finite State Machine

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Wei Li ; Sch. of Comput. Sci. & Technol., Anhui Univ., Hefei ; Yichao Zhang ; Zhengyi Liu ; Jianguo Wu

Controller synthesis uses hardware description language and synthesis optimization tools from a higher abstract level. State transition graph of completely specified finite state machine is adopted to describe the behavior of controller. State transition graph STG_org was generated before synthesized and state transition graph STG_ext was reversely extracted from structure realization of controller synthesis. If STG_org and STG_ext were equivalent then corresponding process of controller synthesis was correct. The paper gives a formal verification algorithm of controller synthesis with time complexity O(B2/Aldrt1(n)+Aldrt2(m,n)) .In order to further improve time complexity of algorithm, a verifying algorithm with synthetic information guidance was proposed. The algorithm is proved efficient in theory for its time complexity is decreased to O(Bldrt1(n) + Aldrt2(m,n)).

Published in:

Information Science and Engineering, 2008. ISISE '08. International Symposium on  (Volume:1 )

Date of Conference:

20-22 Dec. 2008