By Topic

Characteristics of Gate-All-Around Twin Poly-Si Nanowire Thin-Film Transistors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Jeng-Tzong Sheu ; Inst. of Nanotechnol., Nat. Chiao Tung Univ., Hsinchu ; Po-Chun Huang ; Tzu-Shiun Sheu ; Chen-Chia Chen
more authors

We have investigated the characteristics of gate-all-around (GAA) twin polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs). The NW channel and surrounding gate imparted the GAA twin NW TFT with superior channel controllability. Moreover, the combination of the high surface-to-volume ratio of the NW and the split channel structure led to highly efficient NH3 plasma treatment, which reduced the effective grain-boundary trap-state density. The GAA twin NW TFT exhibited greatly improved electrical performance, including a lower threshold voltage, a steeper subthreshold swing (114 mV/dec), a higher on/off current ratio (> 108), and a virtual absence of drain-induced barrier lowering (13 mV/V).

Published in:

IEEE Electron Device Letters  (Volume:30 ,  Issue: 2 )