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FPOAs are reconfigurable devices similar to FPGAs but offer a much higher level of abstraction than the gate level. The main advantage of FPOAs is their deterministic on chip network, which guarantees that an application executes at the design frequency. Mathstarpsilas current toolflow requires constant manual guidance to place and route a design. In this paper we propose a finite domain Constraint Satisfaction (CS) based approach, which considers the communication delay between hardware resources to ensure that they meet the designpsilas timing requirement. We tested our Placement tool using a parameterized design test generator, and a 48-tap FIR filter. The tool reported a feasible solution for problems with known solutions, typically within a few seconds.