By Topic

The Design of a Low-Power Asynchronous DES Coprocessor for Sensor Network Encryption

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Yijun Liu ; Fac. of Comput., Guangdong Univ. of Technol., Guangzhou, China ; Pinghua Chen ; Guobo Xie ; Zhusong Liu
more authors

Sensor network nodes have a very tight power budget and the power efficiency is the biggest design concern in sensor network circuits. A general-purpose processor (e.g. an ARM processor) is not efficient to execute encryption algorithms because it has no special instructions to support encryption operations, for example very often-used permutation operations. In the paper, we propose a low-power ASIC encryption coprocessor for sensor network nodes. A DES algorithm is used because the algorithm does not include power-hungry and complex mathematic operations, such as multiplication, division and addition. An asynchronous logic style is used to design the coprocessor. With an asynchronous controller, a global clock is not necessary when idle, resulting in zero standby dynamic power. Using the DES coprocessor, the power consumed by encryption can be saved by 4 orders of magnitude than a pure software calculation.

Published in:

Computer Science and Computational Technology, 2008. ISCSCT '08. International Symposium on  (Volume:2 )

Date of Conference:

20-22 Dec. 2008