Cart (Loading....) | Create Account
Close category search window

A Full TCAD simulation and 3D parasitic capacitances extraction in 90nm NAND flash memories

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Postel-Pellerin, J. ; IM2NP CNRS, Aix-Marseille Univ., France ; Canet, P. ; Lalande, F. ; Bouchakour, R.
more authors

In this paper we propose a way to study the degradation mechanism of ¿inhibited¿ cells during the cycling of ¿selected¿ cells in 90 nm NAND Flash memories. This degradation is a main issue in NAND Flash memories reliability. To explain this degradation, we first develop a 2D TCAD cell simulation to watch attentively what happens in the channel where measurements are impossible. Some phenomena are shown here which could begin to explain what occurs. Because of continual shrinking, coupling capacitances between cells in the array have a significant impact on the cell behaviour. The previous simulation can be completed by taking into account these 3D parasitic capacitances which have been extracted in a second time.

Published in:

Non-Volatile Memory Technology Symposium, 2008. NVMTS 2008. 9th Annual

Date of Conference:

11-14 Nov. 2008

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.